1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems incorporating a cache memory and for which data processing operations continue, where possible, when a cache miss occurs.
2. Description of the Prior Art
It is known to provide data processing systems having cache memories in order to increase the processing performance of such systems. Cache memories provide a relatively small amount of high speed memory compared with the main memory, such as Random Access Memory (RAM) or disk storage, that provides a comparatively large amount of low speed storage. Whilst efforts are made to provide within the cache memory a copy of the data desired from the main memory, inevitably data access requests occur to data items not currently stored within the cache memory. In such circumstances, a cache xe2x80x9cmissxe2x80x9d is triggered, and typically a linefill operation is performed. A linefill operation selects a victim cache line containing multiple data items from within the cache memory and replaces those data items with data items from a block of memory addresses including the desired data item that gave rise to the cache miss.
In known cache memory systems, such as the Advanced RISC Machines (ARM) ARM920 processor produced by ARM Limited, Cambridge, England, when a cache miss occurs, then the victim cache line is marked as invalid throughout the subsequent linefill operation until the linefill is completed and the new cache line is again marked as valid.
It is an object of the present invention to provide greater processing performance within a data processing system including a processor core and a cache memory.
Viewed from one aspect, the present invention provides an apparatus for processing data, comprising:
a processor core operable to generate a data access request to a target data item having a target memory address;
a cache memory having a plurality of cache lines, each cache line storing a plurality of data items associated with an address value, the cache memory being operable such that:
(i) if the target data item is stored within the cache memory, then said the cache memory is operable to service the data access request; or
(ii) if the target data item is not stored within the cache memory, then the cache memory triggers a cache line fill operation whereby a plurality of new data items including said target data item are fetched from a main memory and written into a victim cache line among the plurality of cache lines replacing any old data items previously stored in the victim cache line; and
a cache controller responsive to one or more status bits associated with the victim cache line to be operable during a cache line fill operation to permit data access requests to those data items stored within the victim cache line associated with a current address value for the victim cache line.
The inventor recognized that during a linefill operation, it is possible to continue using the old data items for some time and also use new data items from a partially completed linefill even though the linefill operation is still pending. Given the relatively long delay incurred by a linefill operation due to the relatively slow access that is possible to the main memory, the processor core and cache memory may be capable of performing a considerable amount of useful processing activity during the linefill operation. The inventor recognized that this processing activity can be extended to include accesses to the victim cache line. As an example, until the first of the new data starts to be returned from the main memory, the old data in the cache line may continue to be made available to the processor core should subsequent data processing operations require that data and there not be any intervening dependency upon the operations that have missed that prevents the subsequent data processing operation from being performed. Thus, the old data in the victim cache line is preferably made available for continued use until its replacement within the cache actually starts.
In a similar manner, as the new data items are streamed back from the main memory, they are written into the victim cache line. It may be that subsequent data processing operations can make use of those data items to carry out useful processing tasks even before the cache linefill has completed.
This ability to continue to work with data items that are subject to a pending cache linefill is further enhanced in embodiments that provide a fill buffer that may be associated with the victim cache line and into which new data values that are intended to overwrite the data values to be read from the main memory may be written even though the data items from the cache miss have not yet been returned.
While it would be possible to associate a plurality of status bits with each cache line indicating the progress through a linefill for that individual cache line, circuit area is saved when each cache line is associated with a cache line status bit that serves to indicate that a linefill is pending for that cache line without in itself giving information about the progress of that particular linefill.
In circumstances in which only a single pending linefill is allowed at any given time, a single set of data item status bits may be provided for the cache memory and serve to indicate the progress through the pending linefill operation with the cache line concerned being identified through another bit.
The bus requirements for storing out dirty cache data can be reduced in preferred embodiments in which the dirty data items are separately removed from the victim cache line as they are replaced by their respective new data items.
In embodiments having both a set of data item status bits and a cache line status bit, preferred embodiments act to first check whether a cache line status bit is set indicating a pending linefill operation and then reference is made to the data item status bits to determine the state of progress of that linefill operation in order to grant or deny permission to a particular data access request being made to the cache memory.
It will be appreciated that the principle of the present invention could be applied to many different types of cache architecture. In particular, the invention is equally applicable to content addressable memory architectures and tag RAM architectures.
In the case of a content addressable memory architecture, it is convenient to include the cache line status bits within the content addressable memory as then the check for a pending linefill operation can be combined with the address matching operation normally performed and provided for as part of the content addressable memory operation.
The invention is particularly well suited for use in systems that provide hit-under-miss operation for their caches and also critical data first linefill operations.
Viewed from another aspect, the present invention provides a method of processing data, the method comprises:
generating a data access request to a target data item having a target memory address;
storing data items in a cache memory having a plurality of cache lines, each cache line storing a plurality data items associated with an address value, the cache memory being operable such that:
(i) if the target data item is stored within the cache memory, then the cache memory is operable to service the data access request; or
(ii) if the target data item is not stored within the cache memory, then the cache memory triggers a cache line fill operation whereby a plurality of new data items including the target data item are fetched from a main memory and written into a victim cache line among the plurality of cache lines replacing any old data items previously stored in the victim cache line; and
in response to one or more status bits associated with the victim cache line, permitting during a cache line fill operation data access requests to those data items stored within said victim cache line associated with a current address value for the victim cache line.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which description is to be read in connection with the accompanying drawings.